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? 2004 microchip technology inc. ds21130e-page 1 93aa76/86 features: ? single supply operation down to 1.8v low-power cmos technology: - 1 ma active current typical -5 a standby current (typical) at 3.0v org pin selectable memory configuration: - 1024 x 8 or 512 x 16-bit organization (93aa76) - 2048 x 8 or 1024 x 16-bit organization (93aa86) self-timed erase and write cycles automatic eral before wral power on/off data protection circuitry industry standard 3-wire serial i/o device status signal during erase/write cycles sequential read function 1,000,000 erase/write cycles ensured data retention > 200 years 8-pin pdip/soic package temperature ranges available: - commercial (c): 0 c to +70 c description: the microchip technology inc. 93aa76/86 are 8k and 16k low voltage serial electrically erasable proms. the device memory is configured as x8 or x16 bits depending on the org pin setup. advanced cmos technology makes these devices ideal for low power nonvolatile memory applications. these devices also have a program enable (pe) pin to allow the user to write-protect the entire contents of the memory array. the 93aa76/86 is available in standard 8-pin pdip and 8-pin surface mount soic packages. package types block diagram soic package pdip package cs clk di do v ss pe v cc org cs clk di do v cc pe org v ss 93aa76/86 93aa76/86 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 do cs clk v cc v ss memory array address decoder data register counter address output buffer mode decode logic generator clock di pe 8k/16k 1.8v microwire serial eeprom not recommended for new designs ? please use 93aa76c or 93aa86c.
93aa76/86 ds21130e-page 2 ? 2004 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ........................................................................................................ -0.6v to vcc + 1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c soldering temperature of leads (10 seconds) .................................................................................... ...................+300c esd protection on all pins ..................................................................................................... .....................................4 kv 1.1 ac test conditions ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ac waveform: v lo = 2.0v v hi = vcc - 0.2v (note 1) v hi = 4.0v for (note 2) timing measurement reference level: input 0.5 v cc output 0.5 v cc note 1: for v cc < 4.0v 2: for v cc > 4.0v
? 2004 microchip technology inc. ds21130e-page 3 93aa76/86 table 1-1: dc characteristics dc characteristics applicable over recommended operating ranges shown below unless otherwise noted: v cc = +1.8v to +6.0v commercial (c): t a = 0c to +70c parameter symbol min. max. units conditions high-level input voltage v ih1 2.0 v cc + 1 v v cc 2.7v v ih2 0.7 v cc v cc + 1 v v cc < 2.7v low-level input voltage v il1 -0.3 0.8 v v cc 2.7v v il2 -0.3 0.2 v cc vv cc < 2.7v low-level output voltage v ol1 ?0.4vi ol = 2.1 ma; v cc = 4.5v v ol2 ?0.2vi ol =100 a; v cc = v cc min. high-level output voltage v oh1 2.4 ? v i oh = -400 a; v cc = 4.5v v oh2 v cc -0.2 ? v i oh = -100 a; v cc = v cc min. input leakage current i li -10 10 av in = 0.1v to v cc output leakage current i lo -10 10 av out = 0.1v to v cc pin capacitance (all inputs/outputs) c int ?7pf (note 1) t a = +25c, f clk = 1 mhz operating current i cc write ? 3 ma v cc = 5.5v i cc read ? 1 500 ma a f clk = 3 mhz; v cc = 5.5v f clk = 1 mhz; v cc = 3.0v standby current i ccs ?100 30 a a clk = cs = 0v; v cc = 5.5v clk = cs = 0v; v cc = 3.0v di = pe = v ss org = v ss or v cc note 1: this parameter is periodically sampled and not 100% tested.
93aa76/86 ds21130e-page 4 ? 2004 microchip technology inc. table 1-2: ac characteristics ac characteristics applicable over recommended operating ranges shown below unless otherwise noted: v cc = +1.8v to +6.0v commercial (c): t a = 0c to +70c parameter symbol min. max. units conditions clock frequency f clk ?3 2 1 mhz mhz mhz 4.5v v cc 6.0v 2.5v v cc 4.5v 1.8v v cc < 2.5v clock high time t ckh 200 300 500 ?ns ns ns 4.5v v cc 6.0v 2.5v v cc < 4.5v 1.8v v cc < 2.5v clock low time t ckl 100 200 500 ?ns ns ns 4.5v v cc 6.0v 2.5v v cc < 4.5v 1.8v v cc < 2.5v chip select setup time t css 50 100 250 ?ns ns ns 4.5v v cc 6.0v, relative to clk 2.5v v cc < 4.5v, relative to clk 1.8v v cc < 2.5v, relative to clk chip select hold time t csh 0 ? ns 1.8v v cc 6.0v chip select low time t csl 250 ? ns 1.8v v cc 6.0v, relative to clk data input setup time t dis 50 100 250 ?ns ns ns 4.5v v cc 6.0v, relative to clk 2.5v v cc <4.5v, relative to clk 1.8v v cc < 2.5v, relative to clk data input hold time t dih 50 100 250 ?ns ns ns 4.5v v cc 6.0v, relative to clk 2.5v v cc < 4.5v, relative to clk 1.8v v cc < 2.5v, relative to clk data output delay time t pd ?100 250 500 ns ns ns 4.5v v cc 6.0v, c l = 100 pf 2.5v v cc < 4.5v, c l = 100 pf 1.8v v cc < 2.5v, c l = 100 pf data output disable time t cz ?100 500 ns ns 4.5v v cc 5.5v (note 1) 1.8v v cc < 4.5v (note 1) status valid time tsv ? 200 300 500 ns ns ns 4.5v v cc 6.0v, c l = 100 pf 2.5v v cc < 4.5v, c l = 100 pf 1.8v v cc < 2.5v, c l = 100 pf program cycle time t wc ? 5 ms erase/write mode t ec ?15mseral mode t wl ? 30 ms wral mode endurance ? 1m ? cycles 25c, v cc = 5.0v, block mode (note 2) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance ? model which can be obtained from microchip?s web site at: www.microchip.com
? 2004 microchip technology inc. ds21130e-page 5 93aa76/86 table 1-3: instruction set for 93aa76: org = 1 (x16 organization) table 1-4: instruction set for 93aa76: org = 0 (x8 organization) table 1-5: instruction set for 93aa86: org = 1 (x16 organization) table 1-6: instruction set for 93aa86: org = 0 (x8 organization) instruction sb opcode address data in data out req. clk cycles read 1 10 x a8 a7 a6 a5 a4 a3 a2 a1 a0 ? d15 - d0 29 ewen 1 00 1 1 x x x x x x x x ? high-z 13 erase 1 11 x a8 a7 a6 a5 a4 a3 a2 a1 a0 ? (rdy/bsy) 13 eral 1 00 1 0 x x x x x x x x ? (rdy/bsy) 13 write 1 01 x a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy) 29 wral 1 00 0 1 x x x x x x x x d15 - d0 (rdy/bsy) 29 ewds 1 00 0 0 x x x x x x x x ? high-z 13 instruction sb opcode address data in data out req. clk cycles read 1 10 x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? d7 - d0 22 ewen 1 00 1 1 x x x x x x x x ? high-z 14 erase 1 11 x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? (rdy/bsy) 14 eral 1 00 1 0 x x x x x x x x ? (rdy/bsy) 14 write 1 01 x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy) 22 wral 1 00 0 1 x x x x x x x x d7 - d0 (rdy/bsy) 22 ewds 1 00 0 0 x x x x x x x x ? high-z 14 instruction sb opcode address data in data out req. clk cycles read 1 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? d15 - d0 29 ewen 1 00 1 1 x x x x x x x x ? high-z 13 erase 1 11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? (rdy/bsy) 13 eral 1 00 1 0 x x x x x x x x ? (rdy/bsy) 13 write 1 01 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy) 29 wral 1 00 0 1 x x x x x x x x d15 - d0 (rdy/bsy) 29 ewds 1 00 0 0 x x x x x x x x ? high-z 13 instruction sb opcode address data in data out req. clk cycles read 1 10 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? d7 - d0 22 ewen 1 00 1 1 x x x x x x x x ? high-z 14 erase 1 11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ? (rdy/bsy) 14 eral 1 00 1 0 x x x x x x x x ? (rdy/bsy) 14 write 1 01 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy) 22 wral 1 00 0 1 x x x x x x x x d7 - d0 (rdy/bsy) 22 ewds 1 00 0 0 x x x x x x x x ? high-z 14
93aa76/86 ds21130e-page 6 ? 2004 microchip technology inc. 2.0 principles of operation when the org pin is connected to v cc , the x16 organization is selected. when it is connected to ground, the x8 organization is selected. instructions, addresses and write data are clocked into the di pin on the rising edge of the clock (clk). the do pin is normally held in a high-z state except when reading data from the device, or when checking the ready/busy status during a programming operation. the ready/busy status can be verified during an erase/write operation by polling the do pin; do low indicates that programming is still in progress, while do high indicates the device is ready. the do will enter the high-impedance state on the falling edge of the cs. 2.1 start condition the start bit is detected by the device if cs and di are both high with respect to the positive edge of clk for the first time. before a start condition is detected, cs, clk and di may change in any combination (except to that of a start condition), without resulting in any device opera- tion (read, write, erase, ewen, ewds, eral and wral). as soon as cs is high, the device is no longer in the standby mode. an instruction following a start condition will only be executed if the required amount of opcode, address and data bits for any particular instruction are clocked in. after execution of an instruction (i.e., clock in or out of the last required address or data bit) clk and di become ?don't care? bits until a new start condition is detected. 2.2 di/do it is possible to connect the data in and data out pins together. however, with this configuration it is possible for a ?bus conflict? to occur during the ?dummy zero? that precedes the read operation, if a0 is a logic high level. under such a condition the voltage level seen at data out is undefined and will depend upon the relative impedances of data out and the signal source driving a0. the higher the current sourcing capability of a0, the higher the voltage at the data out pin. 2.3 erase/write enable and disable (ewen, ewds) the 93aa76/86 powers up in the erase/write disable (ewds) state. all programming modes must be preceded by an erase/write enable ( ewen ) instruction. once the ewen instruction is executed, programming remains enabled until an ewds instruction is executed or v cc is removed from the device. to protect against accidental data disturb, the ewds instruction can be used to disable all erase/write functions and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instructions. 2.4 data protection during power-up, all programming modes of operation are inhibited until v cc has reached a level greater than 1.4v. during power-down, the source data protection circuitry acts to inhibit all programming modes when v cc has fallen below 1.4v. the ewen and ewds commands give additional protection against accidentally programming during normal operation. after power-up, the device is automatically in the ewds mode. therefore, an ewen instruction must be performed before any erase or write instruction can be executed.
? 2004 microchip technology inc. ds21130e-page 7 93aa76/86 3.0 device operation 3.1 read the read instruction outputs the serial data of the addressed memory location on the do pin. a dummy zero bit precedes the 16-bit (x16 organization) or 8-bit (x8 organization) output string. the output data bits will toggle on the rising edge of the clk and are stable after the specified time delay (t pd ). sequential read is possible when cs is held high and clock transitions continue. the memory address pointer will automati- cally increment and output data sequentially. 3.2 erase the erase instruction forces all data bits of the specified address to the logical ? 1 ? state. the self-timed programming cycle is initiated on the rising edge of clk as the last address bit (a0) is clocked in. at this point, the clk, cs and di inputs become ?don?t cares?. the do pin indicates the ready/busy status of the device if the cs is high. the ready/busy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high-impedance state. do at logical ? 0 ? indicates that programming is still in progress. do at logical ? 1 ? indicates that the register at the specified address has been erased and the device is ready for another instruction. the erase cycle takes 3 ms per word (typical). 3.3 write the write instruction is followed by 16 bits (or by 8 bits) of data to be written into the specified address. the self-timed programming cycle is initiated on the rising edge of clk as the last data bit (d0) is clocked in. at this point, the clk, cs and di inputs become ?don?t cares?. the do pin indicates the ready/busy status of the device if the cs is high. the ready/busy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high-impedance state. do at logical ? 0 ? indicates that programming is still in progress. do at logical ? 1 ? indicates that the register at the specified address has been written and the device is ready for another instruction. the write cycle takes 3 ms per word (typical). 3.4 erase all (eral) the eral instruction will erase the entire memory array to the logical ? 1 ? state. the eral cycle is identical to the erase cycle except for the different opcode. the eral cycle is completely self-timed and commences on the rising edge of the last address bit (a0). note that the least significant 8 or 9 address bits are ?don?t care? bits, depending on selection of x16 or x8 mode. clocking of the clk pin is not necessary after the device has entered the self clocking mode. the eral instruction is ensured at vcc = +4.5v to +6.0v. the do pin indicates the ready/busy status of the device if the cs is high. the ready/busy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high-impedance state. do at logical ? 0 ? indicates that programming is still in progress. do at logical ? 1 ? indicates that the entire device has been erased and is ready for another instruction. the eral cycle takes 15 ms maximum (8 ms typical). 3.5 write all (wral) the wral instruction will write the entire memory array with the data specified in the command. the wral cycle is completely self-timed and commences on the rising edge of the last address bit (a0). note that the least significant 8 or 9 address bits are ?don?t cares?, depending on selection of x16 or x8 mode. clocking of the clk pin is not necessary after the device has entered the self clocking mode. the wral command does include an automatic eral cycle for the device. therefore, the wral instruction does not require an eral instruction but the chip must be in the ewen status. the wral instruction is ensured at vcc = +4.5v to +6.0v. the do pin indicates the ready/busy status of the device if the cs is high. the ready/busy status will be displayed on the do pin until the next start bit is received as long as cs is high. bringing the cs low will place the device in standby mode and cause the do pin to enter the high-impedance state. do at logical ? 0 ? indicates that programming is still in progress. do at logical ? 1 ? indicates that the entire device has been written and is ready for another instruction. the wral cycle takes 30 ms maximum (16 ms typical).
93aa76/86 ds21130e-page 8 ? 2004 microchip technology inc. figure 3-1: synchronous data timing figure 3-2: read figure 3-3: ewen the memory automatically cycles to the next register. v ih v il v ih v il v ih v oh v ol v oh v ol v il t sv t dis t pd t dih t css t ckh t ckl t pd t csh t cz t cz cs clk di do do (program) (read) status valid 110 a n a 0 d n d n d 0 d 0 ... ... ... high-impedance t csl cs clk di do 0 cs clk di 111 00 t csl xx ... org = v cc , 8 x?s org = v ss , 9 x?s
? 2004 microchip technology inc. ds21130e-page 9 93aa76/86 figure 3-4: ewds figure 3-5: write figure 3-6: wral 10000 xx ... cs clk di t csl org = v cc , 8 x?s org = v ss , 9 x?s 101 a n a 0 ... d n ... d 0 t wc ready busy high-impedance cs clk di do standby t cz ensured at vcc = +4.5v to +6.0v. 10001 x ... xd n ... d 0 busy ready high-impedance standby cs clk di do org = v cc , 8 x?s org = v ss , 9 x?s t wl t cz
93aa76/86 ds21130e-page 10 ? 2004 microchip technology inc. figure 3-7: erase figure 3-8: eral 11 1 a n ... a 0 t cz high-impedance cs clk di do standby ready busy t wc ... ensured at v cc = +4.5v to +6.0v. org = v cc , 8 x?s org = v ss , 9 x?s 10 010 xx ... cs clk di do t ec t cz high-impedance busy ready standby
? 2004 microchip technology inc. ds21130e-page 11 93aa76/86 4.0 pin descriptions table 4-1: pin function table 4.1 chip select (cs) a high level selects the device. a low level deselects the device and forces it into standby mode. however, a programming cycle which is already initiated will be completed, regardless of the cs input signal. if cs is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. cs must be low for 250 ns minimum (t csl ) between consecutive instructions. if cs is low, the internal control logic is held in a reset status. 4.2 serial clock (clk) the serial clock is used to synchronize the communi- cation between a master device and the 93aa76/86. opcode, address and data bits are clocked in on the positive edge of clk. data bits are also clocked out on the positive edge of clk. clk can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (t ckh ) and clock low time (t ckl ). this gives the controlling master freedom in preparing opcode, address and data. clk is a ?don't care? if cs is low (device deselected). if cs is high, but start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for start condition). clk cycles are not required during the self-timed write (i.e., auto erase/write) cycle. after detection of a start condition the specified number of clock cycles (respectively low-to-high transitions of clk) must be provided. these clock cycles are required to clock in all opcode, address and data bits before an instruction is executed (see table 1-2 through table 1-6 for more details). clk and di then become ?don?t care? inputs waiting for a new start condition to be detected. 4.3 data in (di) data in is used to clock in a start bit, opcode, address and data synchronously with the clk input. 4.4 data out (do) data out is used in the read mode to output data synchronously with the clk input (t pd after the positive edge of clk). this pin also provides ready/busy status information during erase and write cycles. ready/busy status infor- mation is available when cs is high. it will be displayed until the next start bit occurs as long as cs stays high. 4.5 organization (org) when org is connected to v cc , the x16 memory organization is selected. when org is tied to v ss , the x8 memory organization is selected. there is an internal pull-up resistor on the org pin that will select x16 organization when left unconnected. 4.6 program enable (pe) this pin allows the user to enable or disable the ability to write data to the memory array. if the pe pin is floated or tied to v cc , the device can be programmed. if the pe pin is tied to v ss , programming will be inhibited. there is an internal pull-up on this device that enables programming if this pin is left floating. name function cs chip select clk serial data clock di serial data input do serial data output v ss ground org memory configuration pe program enable v cc power supply note: cs must go low between consecutive instructions, except when performing a sequential read (refer to section 3.1 ?read? for more detail on sequential reads).
93aa76/86 ds21130e-page 12 ? 2004 microchip technology inc. 5.0 packaging information 5.1 package marking information xxxxxnnn 8-lead pdip xxxxxxxx yyww 017 example 93aa76 0410 8-lead soic (.150?) xxxxxxxx xxxxyyww nnn example 93aa86 /sn0410 017
? 2004 microchip technology inc. ds21130e-page 13 93aa76/86 8-lead plastic dual in-line (p) ? 300 mil body (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
93aa76/86 ds21130e-page 14 ? 2004 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil body (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2004 microchip technology inc. ds21130e-page 15 93aa76/86 appendix a: revision history revision e added note to page 1 header (not recommended for new designs). added section 5.0: package marking information. added on-line support page. updated document format.
93aa76/86 ds21130e-page 16 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21130e-page 17 93aa76/86 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
93aa76/86 ds21130e-page 18 ? 2004 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21130e 93aa76/86 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. ds21130e-page 19 93aa76/86 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx xxx pattern package temperature range device device 93aa76/86: microwire serial eeprom 93aa76/86t: microwire serial eeprom (tape and reel) temperature range blank = 0 c to +70 c package p = pdip sn = plastic soic (150) mil body), 8-lead data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
93aa76/86 ds21130e-page 20 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21130e-page 21 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds21130e-page 22 ? 2004 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 san jose 1300 terra bella avenue mountain view, ca 94043 tel: 650-215-1444 fax: 650-961-0286 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 706b wan tai bei hai bldg. no. 6 chaoyangmen bei str. beijing, 100027, china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building, no. 2 fengxiangnan road, ronggui town, shunde district, foshan city, guangdong 528303, china tel: 86-757-28395507 fax: 86-757-28395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-22290061 fax: 91-80-22290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands waegenburghtplein 4 nl-5152 jr, drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 05/28/04 w orldwide s ales and s ervice

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